The present invention generally relates to semiconductor devices and circuits and methods for fabricating semiconductor devices and circuits, and more particularly to metal-oxide-semiconductor (MOS) field effect transistors (FETs) that incorporate a current sensor.
Metal-oxide-semiconductor field effect transistors (MOSFETs) are much used in modern electronics as individual devices and as part of various integrated circuits (ICs). Particularly demanding applications of MOSFETs occur where they are intended to control large amounts of power, e.g., heavy currents. This type of MOSFET is generally referred to as a “power MOSFET”. It is known to incorporate a current sensor within a power MOSFET to provide a measurement of the amount of current being conducted by the power MOSFET. In many cases, the output of the current sensor is used to limit the current being conducted by the power MOSFET so that the power MOSFET is protected from damage from over-current conditions. Comparatively small MOSFETs are widely used as current sensing devices for power MOSFETs. For convenience, such devices are referred to as sensing FETs or SFETs. Such SFETs may also be referred to as “mirror” devices. In general, the SFET and the power MOSFET share common gate and drain terminals, but independent source terminals. In this way, the current flowing through the source terminal of the SFET can provide a measure of the current flowing through the source terminal of the power MOSFET. For convenience, the main part of the power MOSFET (not counting the SFET) is referred to herein as the “main FET” or MFET.
An important parameter of an SFET is what is referred to as the current sense ratio (CSR), that is, the ratio between the current flowing through the SFET current sensor to the current flowing through the MFET when subjected to substantially the same terminal voltages. In general, the CSR is a property of the device geometry, as for example, the ratio of the active area of the two devices, a ratio that is defined when the devices are designed. However, the CRS is affected by more than just device geometry. For example, the CSR can vary as a function of the temperatures of the main and sensing devices. It is known that the temperature variation in a CSR can be reduced by placing the SFET on the same die or chip or other substrate as the power MOSFET itself so that they are thermally coupled and tend to maintain similar temperatures. The thermal coupling is maximized by placing the SFET within rather than alongside the MFET. However, in that case, electrical isolation of the SFET and the MFET is difficult. In the prior art, such electrical isolation has typically been achieved by placing various doped regions or other forms of isolation walls or combinations thereof between the SFET and the MFET. However, this can significantly increase the overall device area and hence its cost. Accordingly, a need continues to exist for improved power MOSFETs incorporating MFETs and SFETs, and manufacturing methods therefor, in which the area devoted to electrical isolation between the MFET and SFET is reduced or minimized.